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M.Sc. Thesis Presentation: Yue Yi, Dept. of Electrical & Computer Eng.
Start Date: 2/14/2019Start Time: 10:30 AM
End Date: 2/14/2019End Time: 12:30 PM
Event Description:

Dept. of Electrical & Computer Engineering
M.Sc. Thesis Presentation

Yue Yi

FPGA Implementation of
Impedance-Compensated Phase-Locked Loop



Date:
Thursday, 14 Feb 2019

Place: E2-361 EITC Bldg., Ft. Garry Campus

Time: 10:30 AM

 

Examining Committee

Dr. A. Gole, Dept. of Elec. & Comp. Eng., Advisor

Dr. J. Zhou, Dept. of Elec. & Comp. Eng.

Dr. C. K. Leung, Dept. of Computer Science

 

 


Location Information:
University of Manitoba - Fort Garry  (View Map)
University of Manitoba - Fort Garry
Winnipeg, MB
Canada

University of Manitoba - Fort Garry - EITC E2  (View Map)
75 Chancellors Circle
Winnipeg, MB

University of Manitoba - Fort Garry - EITC E2  (View Map)
75 Chancellors Circle
Winnipeg, MB
Room: 361

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